Blab Tech
Indias Semicon 2.0 Sets Up Co-Investment Model to Boost Advanced Chip Design
India’s next big push into the high‑end chip arena arrives today as the Union Cabinet approved the Semicon 2.0 programme on 15 July 2026. The six‑year initiative carries a budget of ₹1.27 lakh crore—roughly US$14 billion—and is designed to strengthen the country’s semiconductor design ecosystem, with a particular emphasis on advanced chips that use 7‑nanometre (nm) nodes and smaller.
Under the plan, the government will provide incentives in the form of grants, equity participation or royalty‑linked payments. The Ministry of Electronics and Information Technology (MeitY) clarified that it will not cap the total amount that can be invested in advanced chip design. Instead, it will partner with venture‑capital firms willing to put money into promising projects. Secretary S Krishnan explained that the existing design‑linked incentive scheme offers about ₹15 crore per project, while high‑end chips often require investments of ₹1,000 crore or more. The co‑investment model is meant to raise overall funding and to leverage private investors’ expertise in project selection.
The policy also acknowledges that India is not yet ready to manufacture advanced chips. Krishnan noted that the nation’s first chip‑fabrication unit will start with a 28‑nm node, which is typically used for power‑electronics applications. Consequently, Semicon 2.0 focuses on design and intellectual‑property creation, positioning India as a key player in the global semiconductor IP market.
To kick‑off the initiative, the ministry has identified 105 startups already working on chip design. The programme will support the development of integrated‑circuit designs—including digital and analog ICs—and will provide resources for research and training. This effort is part of a broader strategy to reduce India’s dependence on imported chips and to bolster the country’s ambitions in artificial intelligence and other high‑technology sectors.
Krishnan emphasized that the government’s role is to co‑invest rather than act as the sole selector of projects. "The idea of co‑investment is two‑fold," he said. "First, it increases the overall funding that is available. Second, the government does not have the capacity to select projects on its own; when a whitelisted venture‑capital fund invests, we will co‑invest." The policy therefore relies on private capital to identify and support the most promising design projects.
The programme’s six‑year timeline begins in the fiscal year 2027. While the policy does not yet include manufacturing incentives, it signals a long‑term commitment to building a domestic ecosystem that can eventually support the full semiconductor value chain. The focus on advanced design is intended to position India as a source of high‑performance chips for artificial‑intelligence workloads and other data‑intensive applications.
In short, Semicon 2.0 combines government grants, equity participation and royalty‑based incentives with private‑sector co‑investment. The initiative aims to scale up the design of advanced chips, support 105 identified startups, and ultimately establish India as a major player in the global semiconductor IP market. Its success will hinge on Indian firms’ ability to secure private investment, the effectiveness of the co‑investment model, and the continued development of design‑related skills and infrastructure. The next few years will see the rollout of funding mechanisms, the selection of projects, and the establishment of design centres that will drive India’s semiconductor ambitions forward.
Under the plan, the government will provide incentives in the form of grants, equity participation or royalty‑linked payments. The Ministry of Electronics and Information Technology (MeitY) clarified that it will not cap the total amount that can be invested in advanced chip design. Instead, it will partner with venture‑capital firms willing to put money into promising projects. Secretary S Krishnan explained that the existing design‑linked incentive scheme offers about ₹15 crore per project, while high‑end chips often require investments of ₹1,000 crore or more. The co‑investment model is meant to raise overall funding and to leverage private investors’ expertise in project selection.
The policy also acknowledges that India is not yet ready to manufacture advanced chips. Krishnan noted that the nation’s first chip‑fabrication unit will start with a 28‑nm node, which is typically used for power‑electronics applications. Consequently, Semicon 2.0 focuses on design and intellectual‑property creation, positioning India as a key player in the global semiconductor IP market.
To kick‑off the initiative, the ministry has identified 105 startups already working on chip design. The programme will support the development of integrated‑circuit designs—including digital and analog ICs—and will provide resources for research and training. This effort is part of a broader strategy to reduce India’s dependence on imported chips and to bolster the country’s ambitions in artificial intelligence and other high‑technology sectors.
Krishnan emphasized that the government’s role is to co‑invest rather than act as the sole selector of projects. "The idea of co‑investment is two‑fold," he said. "First, it increases the overall funding that is available. Second, the government does not have the capacity to select projects on its own; when a whitelisted venture‑capital fund invests, we will co‑invest." The policy therefore relies on private capital to identify and support the most promising design projects.
The programme’s six‑year timeline begins in the fiscal year 2027. While the policy does not yet include manufacturing incentives, it signals a long‑term commitment to building a domestic ecosystem that can eventually support the full semiconductor value chain. The focus on advanced design is intended to position India as a source of high‑performance chips for artificial‑intelligence workloads and other data‑intensive applications.
In short, Semicon 2.0 combines government grants, equity participation and royalty‑based incentives with private‑sector co‑investment. The initiative aims to scale up the design of advanced chips, support 105 identified startups, and ultimately establish India as a major player in the global semiconductor IP market. Its success will hinge on Indian firms’ ability to secure private investment, the effectiveness of the co‑investment model, and the continued development of design‑related skills and infrastructure. The next few years will see the rollout of funding mechanisms, the selection of projects, and the establishment of design centres that will drive India’s semiconductor ambitions forward.
