Blab Tech
Synergy Quantum Unveils Quantum-Safe Silicon IP for RISC-V SoCs
On June 18 2026, in New Delhi, Synergy Quantum announced a comprehensive portfolio of quantum‑safe silicon IP cores tailored for RISC‑V‑based system‑on‑chip (SoC) designs. The cores deliver hardware acceleration for post‑quantum cryptographic algorithms and a suite of security functions—including secure boot, device identity, firmware verification, and remote attestation.
The launch arrives amid rapid RISC‑V adoption across embedded, industrial, automotive, telecom, and defence sectors. Many of these devices are expected to operate for decades, so their security architectures must evolve from classical to quantum‑resistant cryptography without a full system redesign.
According to the press release, the portfolio supports several NIST‑standardised post‑quantum primitives: ML‑KEM for key establishment, ML‑DSA for digital signatures, SLH‑DSA and LMS for hash‑based signatures, and HQC for algorithm diversity. It also incorporates SHA‑3, Keccak, Ascon authenticated encryption, shared number‑theoretic transform (NTT) acceleration, secure boot, post‑quantum firmware‑signature verification, hardware‑enforced anti‑rollback, PUF‑derived device identity, DICE‑style attestation, protected key derivation, key sealing, and hybrid classical‑post‑quantum operation.
The cores are designed to fit as dedicated security components, cryptographic coprocessors, or building blocks within a broader hardware root‑of‑trust subsystem. They can be assembled into a complete quantum‑safe security subsystem or used individually, depending on a product’s performance, power, silicon‑area, and security requirements. The architecture is compatible with industry‑standard SoC interconnects and processor‑extension interfaces, enabling integration into existing RISC‑V processors without a full redesign.
The design couples programmable RISC‑V control with isolated cryptographic datapaths. Software or firmware governs security policies and protocol handling, while the hardware executes the most compute‑intensive and security‑critical operations. This separation permits secure firmware updates, quantum‑safe secure boot, device onboarding, remote attestation, hardware‑protected signing and verification, VPN acceleration, TLS and other network‑security protocols, and protected key release to authorised firmware.
Crypto agility is a key feature. Shared NTT and Keccak engines can be reused across multiple lattice‑based algorithms, reducing duplication. The architecture supports controlled cryptographic updates and hardware‑enforced anti‑rollback, allowing manufacturers to adapt to new standards without replacing the entire device.
Protection against implementation‑level attacks is also addressed. Options include constant‑time execution, masked arithmetic, isolated masking‑value generation, protected handling of intermediate values, hardware‑enforced sequencing, secure zeroisation, PUF‑bound key derivation, boot‑state measurement, firmware anti‑rollback enforcement, and tamper‑aware attestation workflows.
Synergy Quantum said the IP portfolio is aimed at a broad set of stakeholders: RISC‑V processor and SoC developers, semiconductor manufacturers, foundries, FPGA developers, defence and aerospace electronics, telecom and network‑equipment makers, industrial and operational‑technology vendors, automotive and autonomous‑system developers, IoT and embedded‑device manufacturers, and cloud, data‑centre and security‑appliance providers.
The portfolio complements the company’s SynQ Silicon Trust Suite, which provides a system‑level framework for secure boot, key custody, device identity, signing, attestation and policy enforcement. Together they offer a vertically integrated solution that spans quantum‑safe cryptographic hardware, RISC‑V integration, hardware‑rooted identity, protected key lifecycle, device and workload attestation, and enterprise‑level trust services.
"RISC‑V gives semiconductor developers the flexibility to build processors and systems around their own requirements. Quantum‑safe security must become part of that flexibility and must be available as a native silicon capability rather than an afterthought added at the software layer. Synergy Quantum’s quantum‑safe silicon IP cores are designed to help RISC‑V developers integrate post‑quantum cryptography, secure boot, device identity and hardware‑rooted trust directly into the SoC architecture," said Jay Oberai, founder of Synergy Quantum.
This announcement marks the first publicly disclosed silicon implementation of a broad set of post‑quantum primitives for RISC‑V. While the company has not yet released performance or silicon‑area metrics, it has indicated that the cores can be tuned for low‑power IoT devices or high‑throughput telecom and data‑centre applications. No regulatory filings or court actions are associated with the release, and the company has not announced a commercial launch date.
Synergy Quantum’s offering is positioned to support the long‑term migration of embedded and critical‑infrastructure devices to quantum‑resistant cryptography, providing a hardware foundation that can evolve with emerging standards and threat models.
The launch arrives amid rapid RISC‑V adoption across embedded, industrial, automotive, telecom, and defence sectors. Many of these devices are expected to operate for decades, so their security architectures must evolve from classical to quantum‑resistant cryptography without a full system redesign.
According to the press release, the portfolio supports several NIST‑standardised post‑quantum primitives: ML‑KEM for key establishment, ML‑DSA for digital signatures, SLH‑DSA and LMS for hash‑based signatures, and HQC for algorithm diversity. It also incorporates SHA‑3, Keccak, Ascon authenticated encryption, shared number‑theoretic transform (NTT) acceleration, secure boot, post‑quantum firmware‑signature verification, hardware‑enforced anti‑rollback, PUF‑derived device identity, DICE‑style attestation, protected key derivation, key sealing, and hybrid classical‑post‑quantum operation.
The cores are designed to fit as dedicated security components, cryptographic coprocessors, or building blocks within a broader hardware root‑of‑trust subsystem. They can be assembled into a complete quantum‑safe security subsystem or used individually, depending on a product’s performance, power, silicon‑area, and security requirements. The architecture is compatible with industry‑standard SoC interconnects and processor‑extension interfaces, enabling integration into existing RISC‑V processors without a full redesign.
The design couples programmable RISC‑V control with isolated cryptographic datapaths. Software or firmware governs security policies and protocol handling, while the hardware executes the most compute‑intensive and security‑critical operations. This separation permits secure firmware updates, quantum‑safe secure boot, device onboarding, remote attestation, hardware‑protected signing and verification, VPN acceleration, TLS and other network‑security protocols, and protected key release to authorised firmware.
Crypto agility is a key feature. Shared NTT and Keccak engines can be reused across multiple lattice‑based algorithms, reducing duplication. The architecture supports controlled cryptographic updates and hardware‑enforced anti‑rollback, allowing manufacturers to adapt to new standards without replacing the entire device.
Protection against implementation‑level attacks is also addressed. Options include constant‑time execution, masked arithmetic, isolated masking‑value generation, protected handling of intermediate values, hardware‑enforced sequencing, secure zeroisation, PUF‑bound key derivation, boot‑state measurement, firmware anti‑rollback enforcement, and tamper‑aware attestation workflows.
Synergy Quantum said the IP portfolio is aimed at a broad set of stakeholders: RISC‑V processor and SoC developers, semiconductor manufacturers, foundries, FPGA developers, defence and aerospace electronics, telecom and network‑equipment makers, industrial and operational‑technology vendors, automotive and autonomous‑system developers, IoT and embedded‑device manufacturers, and cloud, data‑centre and security‑appliance providers.
The portfolio complements the company’s SynQ Silicon Trust Suite, which provides a system‑level framework for secure boot, key custody, device identity, signing, attestation and policy enforcement. Together they offer a vertically integrated solution that spans quantum‑safe cryptographic hardware, RISC‑V integration, hardware‑rooted identity, protected key lifecycle, device and workload attestation, and enterprise‑level trust services.
"RISC‑V gives semiconductor developers the flexibility to build processors and systems around their own requirements. Quantum‑safe security must become part of that flexibility and must be available as a native silicon capability rather than an afterthought added at the software layer. Synergy Quantum’s quantum‑safe silicon IP cores are designed to help RISC‑V developers integrate post‑quantum cryptography, secure boot, device identity and hardware‑rooted trust directly into the SoC architecture," said Jay Oberai, founder of Synergy Quantum.
This announcement marks the first publicly disclosed silicon implementation of a broad set of post‑quantum primitives for RISC‑V. While the company has not yet released performance or silicon‑area metrics, it has indicated that the cores can be tuned for low‑power IoT devices or high‑throughput telecom and data‑centre applications. No regulatory filings or court actions are associated with the release, and the company has not announced a commercial launch date.
Synergy Quantum’s offering is positioned to support the long‑term migration of embedded and critical‑infrastructure devices to quantum‑resistant cryptography, providing a hardware foundation that can evolve with emerging standards and threat models.
